Peripheral Component Interconnect Express (PCIe) is a third generation Input Output (3GIO) system that implements a serial, switched-packet, point-to-point communication standard at the system level. PCI Express has achieved many advantages over the prior shared bus system, such as quality of service (QoS), high speed peer-to-peer communication between external devices, adaptability, and low pin counts. The basic PCI Express architecture includes a root complex, optionally, a PCI Express switch, and PCI Express endpoints.
In the prior art implementation of a PCI Express switch for routing incoming data packets between root complex and endpoint devices, the transaction layer packet (TLP) routing functions of the switch are hard-coded into the switch. Hard-coding of the switch routing functions is performed during the initial silicon fabrication. If errors are made in the hard-coding of the routing functions during the fabrication process, new revisions of silicon are required to correct the errors. Additionally, if new routing function features are to be added to the device, it would be necessary to fabricate a new revision of the silicon to incorporate the new features. Fabricating new revisions of silicon is an expensive and time-consuming process which undesirably delays the device time-to-market. As the PCIe standard matures it may also be necessary to implement non-standard routing features that may not be included in the standard PCIe devices.
Thus, there is a need for a method and apparatus that will reduce the cost of implementing changes to the TLP routing function of the PCI Express device after initial fabrication of the silicon and that will also reduce the time delay required to implement the changes to the routing function. Additionally, there is a need in the art for implementing non-standard features of PCIe devices into a PCIe switch.